This invention relates to the design of electronic circuit cards. Specifically, it is directed to the problem of electrically decoupling a BGA device with surface mount capacitors placed on the opposite side of the circuit card with respect to the BGA device and within the grid of vias and contacts used to route signal traces to and from the BGA device.
A number of solutions have been previously developed. These solutions targeted at solving decoupling issues on 1.00 mm pitch BGA devices. However these solutions are not applicable to finer pitch BGA devices (<1.00 mm). Increasing design densities and component miniaturization trends are making the use of 0.8 mm BGAs more common on many designs.
Referring to FIGS. 1A-1C, this prior art approach uses shared vias on power SP and ground SG connections aligned in columns, in order to form a routing channel (i.e. a larger space between the row of shared vias SV and an adjacent row) through which connections can be routed. This is not a decoupling solution, however the assignee hereof has filed a patent application on a solution that makes use of the shared via SV concept. That patent application is U.S. Ser. No. 10/761,343 entitled “Shared Via Decoupling for Area Arrays Components” and was filed on Jan. 22, 2004 and is incorporated herein by reference. FIG. 1C illustrates an example of this “shared-via” decoupling technique. The main drawback of the shared-via solution is that it is not always possible to share vias even though there are alternating power and ground rows. For example, in some cases the combined transient current of two power supply balls may exceed the limit for a via, in which case the two balls cannot share a via, and consequently the shared-via decoupling technique for those balls cannot be used.
Referring to prior art FIG. 2, the off-grid decoupling solution required to shift the grid of the vias in the 1 mm pitch BGA device in order to create space to allow the 0402 capacitor PC to fit into the space. Such technique will not be able to apply to a 0.8 mm pitch device without violating the spacing requirement between conductive features.
The object of the present invention is to provide a novel decoupling solution that seeks to address decoupling of sub-1 mm pitch BGAs (specifically, devices with a pitch of 0.8 mm×1 mm and 0.8 mm×0.8 mm).
This invention uses octagonal land patterns in combination with specifically filled vias underneath fine pitch BGA devices for decoupling applications.
The focus of this solution is to provide decoupling for 0.8 mm×0.8 mm pitch and 0.8 mm×1 mm pitch fine pitch BGA devices.
The idea of merging the use of new PCB technology with a novel land pattern design will allow the population of capacitors directly underneath fine pitch BGA devices, something which was not possible previously.